Ultra-violet protected tamper resistant embedded EEPROM

ABSTRACT

A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.

RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent applicationSer. No. 11/065,312 entitled “Protection Against In-Process Charging InSilicon-Oxide-Nitride-Oxide-Silicon (SONOS) Memories” filed Feb. 23,2005, which is a divisional of U.S. patent application Ser. No.10/659,031 entitled “Protection Against In-Process Charging InSilicon-Oxide-Nitride-Oxide-Silicon (SONOS) Memories” filed Sep. 9,2003.

FIELD OF THE INVENTION

The present invention relates to a method for decreasing the influenceof external UV light on a floating gate electrode in a semiconductordevice which uses this electrode for storing information as electricalcharges.

RELATED ART

Non-volatile memory (NVM) cells, such as electrically erasableprogrammable read only memory (EEPROM) cells, which store charge inpolycrystalline silicon (polysilicon) floating gate structures aresusceptible to ultra-violet (UV) radiation having quanta energy greaterthan 3.2 electron-Volts (eV). More specifically, because the potentialbarrier for electrons at a silicon oxide-silicon (SiO—Si) interface is3.2 eV, UV radiation having a quanta energy greater than 3.2 eV cancause electrons to be removed from a polysilicon floating gate through asilicon oxide layer. UV irradiation can therefore undesirably cause thecharge state of a polysilicon floating gate to change, such thatinformation stored in the polysilicon floating gate is lost.

The back end layers of most EEPROM devices are at least partiallytransparent in the dangerous UV range. For example, many conventionalback end layers (i.e., layers of a multi-layer interconnect structure)contain silicon oxide, silicon nitride and/or silicon oxynitride. Suchlayers are transparent to UV radiation. A patterned metal layer may beused to provide some UV protection. However, such protection will belimited, due to the relatively large distance between the patternedmetal layer and the underlying polysilicon floating gate structures.This relatively large distance allows significant light penetrationthrough gaps in the patterned metal layer. In addition, an additionalmask must be added to the back end process flow in order to create thepatterned metal layer. Moreover, the patterned metal layer undesirablyintroduces high parasitic capacitances to the interconnect structure.

EEPROM cells that are included in a package-less integrated circuit or achip packaged in a UV transparent (or partially transparent) package canabsorb significant amounts of UV radiation, even when exposed to naturalsunlight. Such UV exposure may occur in radio frequency identification(RFID) or smart card products, where the EEPROM containing dice aredirectly attached to a transparent sticker or a plastic card. Thissituation is especially dangerous when products with RFID tags arestored close to strong UV sources (e.g., exposed to sunlight, or locatednear arc welding facilities or certain luminescent lamps).

A common tamper attack method, wherein illegal reading is performed fromembedded EEPROM products, consists of local irradiation of EEPROM cells(typically from the front side) in combination with a varied (decreased)power supply voltage. This technique enables the programmed and erasedbits of the EEPROM cells to be distinguished by simply controlling thechip functionality. In some cases, it is possible to change informationstored by the embedded EEPROM products. It is especially critical toprevent the changing of information for smart cards, which may storepersonal and/or financial information. The UV tamper attack technique isnon-invasive and can be applied to embedded EEPROM cells that do nothave special tamper protecting designs. The UV tamper attack techniqueis especially effective for RFID chips that include EEPROM cellsfabricated within a single polysilicon layer technology and having alarge cell periphery (i.e., tens of microns).

A layer of organic polymer, such as polyimid, can be added over the topof the back end dielectric stack. This organic polymer layer ispatterned to allow electrical contacts to the device bond pads. Theorganic polymer layer might have a composition that renders this layernot transparent to UV radiation. However, the formation and patterningof an organic polymer layer adds costly process steps, prevents scalingof the dimensions of the bond pad openings, and is non-standard inadvanced sub-micron VLSI processes. Moreover, the organic polymer layeris easily removed in acid, without etching the pads, and thus fails tocomplicate tampering attacks.

It would therefore be desirable to have a tamper resistant system for adevice that implements EEPROM cells fabricated with a single gate layer.It would further be desirable if the processes required to fabricatesuch a device were highly compatible with conventional fabricationprocesses (e.g., would not require the use of additional mask steps).

SUMMARY

Accordingly, the present invention provides an improved back endstructure for a non-volatile memory cell that includes a polysiliconfloating gate. The back end structure of the present invention is mostbeneficial when the non-volatile memory cell is fabricated using asingle polysilicon layer.

In accordance with one embodiment, the back end structure includes alight absorbing layer, which prevents UV radiation from reaching thepolysilicon floating gate. In a preferred embodiment, the lightabsorbing layer is included in a pre-metal dielectric layer locatedbetween the polysilicon floating gate and the first metal layer, therebypreventing the polysilicon floating gate from being electronicallydischarged in response to UV irradiation. In other embodiments, thelight absorbing layer is included in an inter-metal dielectric layer.The requirements/desirable properties of the light-absorbing layer areas follows. First, the light-absorbing layer must efficiently block UVlight. Second, the fabrication of the light-absorbing layer should becompatible with a core VLSI process. Third, the light-absorbing layershould only require minimum changes to the memory array parameters. Forexample, the light-absorbing layer should only introduce a minimumcapacitive coupling to the memory array. Fourth, the light-absorbinglayer should require a minimum number of additional masks. Fifth, thelight-absorbing layer should be electrically non-conductive. In oneembodiment, the light-absorbing layer is amorphous silicon.

In accordance with one embodiment, a non-volatile memory structureincludes a semiconductor substrate, a plurality of polysilicon floatinggates formed over the semiconductor substrate, and a pluralitypolysilicon control gates formed over the semiconductor substrate. Inone embodiment, the floating gates and control gates are formed from thesame polysilicon layer. A thin silicon nitride barrier layer is formedover the resulting structure, in accordance with conventional processingtechniques. A first pre-metal dielectric layer is formed over thesilicon nitride barrier layer. This first pre-metal dielectric layer canbe, for example, USG or BPSG. The light-absorbing layer is then formedover the first pre-metal dielectric layer. A second pre-metal dielectriclayer is then formed over the light-absorbing layer. The secondpre-metal dielectric layer can be, for example, BPSG.

A photoresist mask, which defines the locations of the various contacts,is then formed over the second pre-metal dielectric layer. An etch isperformed through the photoresist mask, thereby creating contactopenings through the second pre-metal dielectric layer, thelight-absorbing layer and the first pre-metal dielectric layer. Thisetch is stopped on the silicon nitride barrier layer.

In one embodiment an oxidation step is then performed, thereby creatingan insulating oxide on the exposed sidewalls of the light-absorbinglayer. In another embodiment, a chemical vapor deposition (CVD)dielectric layer is formed on the exposed sidewalls of thelight-absorbing layer. In yet another embodiment, both the insulatingoxide and the CVD dielectric layer are formed. The exposed portions ofthe silicon nitride barrier layer in the contact openings are thenremoved.

The contact openings are subsequently filled with a contact metal, suchas tungsten or aluminum. In one embodiment, the contacts are isolatedfrom the light-absorbing layer by the insulating oxide and/or the CVDdielectric layer formed on the exposed sidewalls of the light-absorbinglayer. In another embodiment, the specific resistance of thelight-absorbing layer (e.g., amorphous silicon) is high enough (e.g.,greater than about 10⁹ Ohm/sq at maximum operation temperature) that nodielectric material is required on the exposed sidewalls of thelight-absorbing layer.

The present invention will be more fully understood in view of thefollowing description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a single-poly NVM cell, which is used toillustrate one embodiment of the present invention.

FIG. 2 is a cross sectional view along section line A-A of thesingle-poly NVM cell of FIG. 1.

FIGS. 3A, 3B, 3C, 3D and 3E are cross sectional views along section lineA-A of FIG. 1 during various process steps in accordance with oneembodiment of the present invention.

FIGS. 4A and 4B are cross-sectional views along section line A-A of FIG.1 during various process steps in accordance with one variation of theembodiment of FIGS. 3A-3E.

FIGS. 5A, 5B and 5C are cross-sectional views along section line A-A ofFIG. 1 during various process steps in accordance with another variationof the embodiment of FIGS. 3A-3E.

FIG. 6 is a cross-sectional view of a single-poly EEPROM cell formed bycombining the variations of FIGS. 4A-4B and 5A-5C.

FIGS. 7A, 7B, 7C and 7D are cross-sectional views along section line A-Aof FIG. 1 during various process steps in accordance with a secondembodiment of the present invention.

DETAILED DESCRIPTION

FIG. 1 is a top view of a single-poly non-volatile memory (NVM) cell100, which is used to illustrate one embodiment of the presentinvention. As used herein, a single-poly NVM cell includes any NVM cellfabricated with a single gate layer. This single gate layer can be usedto form the control gate and floating gate of the NVM cell, as well asthe control gate of any other transistor fabricated on the same wafer.In the described embodiments, single-poly NVM cell 1000 is anelectrically programmable erasable read only memory (EEPROM) cell.EEPROM cell 100 includes a p-channel NVM transistor 110 formed in ann-well region 115, and an n-channel NVM transistor 120 and a selecttransistor 150 formed in a p-well region 125. In addition, a metalstructure 160 is connected between drain regions of p-channel transistor110 and n-channel transistor 120. A floating gate 130 and a control gate140 of EEPROM cell 100 are fabricated using a single polysilicon layerand arranged in an inter-digitated manner. In particular, floating gate130 includes a first floating gate portion 130-1 formed over a channelof p-channel transistor 110 and a second floating gate portion 130-2formed over a channel of n-channel transistor 120. In addition, floatinggate 130 includes a third portion 130-3 that extends from the firstfloating gate portion 130-1 and extends along a first portion 140-1 ofcontrol gate 140. Floating gate 130 also includes a fourth portion 130-4that extends from second floating gate portion 130-2 and extends along asecond portion 140-2 of control gate 140. Moreover, control gate 140includes a finger (third) portion 140-3 that extends into a channelformed by third portion 130-3 and fourth portion 130-4. By varying thedistance between these portions of floating gate 130 and control gate140, a capacitive coupling Cc is established that facilitates operationof EEPROM cell 100.

FIG. 2 is a cross sectional view of EEPROM cell 100 along section lineA-A of FIG. 1. Additional elements shown in FIG. 2 includemonocrystalline silicon substrate 101, field dielectric region 102, gatedielectric layer 103 and dielectric sidewall material 104. The operationand design of EEPROM cell 100 is described in more detail in U.S. Pat.No. 6,788,576 to Roizin et al., which is hereby incorporated byreference.

The present invention will now be described with respect to thesingle-poly EEPROM cell 100 of FIG. 1. Although the present invention isdescribed with respect to a single-poly EEPROM cell 100, it isunderstood that the present invention is also applicable to other memorystructures which include a floating storage element that would otherwisebe subject to exposure to significant UV radiation, e.g., a double-polymemory cell. Moreover, although only one single-poly EEPROM cell 100 isillustrated, one of ordinary skill in the art would understand that aplurality of these memory cells may be configured to form an array.

As described in more detail below, a pre-metal dielectric structure,which includes a light-absorbing structure, is formed over single-polyEEPROM cell 100. This light-absorbing structure blocks UV radiation fromreaching substrate 101 during subsequent processing steps (i.e., duringformation of a multi-layer interconnect structure) and during operationof EEPROM cell 100. As a result, the UV radiation cannot causesignificant electronic charge to be transferred between the floatinggate 130 to the control gate 140, or between 140 and n-well 115 andp-well 125).

The fabrication of an overlying multi-layer interconnect structure inaccordance with one embodiment of the present invention will now bedescribed.

FIGS. 3A-3E are cross sectional views of EEPROM cell 100 along sectionline A-A of FIG. 1 during various process steps. The single-poly EEPROMcell 100 as illustrated in FIGS. 1 and 2 is initially fabricated usingwell known semiconductor processing steps.

As shown in FIG. 3A, a thin dielectric barrier layer 301 can be formedover the resulting structure. In the described embodiment, dielectricbarrier layer 301 is a silicon nitride layer having a thickness in therange of 100 to 400 Angstroms.

A first pre-metal dielectric layer 311 is then formed over siliconnitride barrier layer 301, as illustrated in FIG. 3A. In the describedembodiment, pre-metal dielectric layer 311 is USG or BPSG, deposited toa thickness in the range of 500 to 8000 Angstroms. However, otherdielectric materials, having other thicknesses can be used in otherembodiments. In accordance with the illustrated embodiment, the uppersurface of pre-metal dielectric layer 311 is planarized (e.g., bychemical mechanical polishing (CMP)). However, such planarization is notprincipal in the discussed embodiments.

As illustrated in FIG. 3B, a light-absorbing layer 312 is formed overfirst pre-metal dielectric layer 311. In the described embodiment,light-absorbing layer 312 is a layer of amorphous silicon having athickness in the range of about 400 to 2000 Angstroms. Otherlight-absorbing layers can be used in other embodiments. When amorphoussilicon layer 312 has a thickness greater than about 1000 Angstroms,this layer will show negligible UV penetration for all practical sourcesof UV radiation. Advantageously, amorphous silicon is a very highresistance semiconductor. In addition, amorphous silicon is compatiblewith conventional semiconductor processes and does not introducesignificant capacitance to the pre-metal dielectric structure.Advantageously, amorphous silicon is a very high resistancesemiconductor.

A second pre-metal dielectric layer 313 is formed over light-absorbinglayer 312, as illustrated in FIG. 3B. In the described embodiment,pre-metal dielectric layer 313 can be BPSG deposited to a thickness inthe range of 500 to 8000 Angstroms. Other dielectric materials can beused to form second pre-metal dielectric layer 313 in other embodiments.The combined thickness of layers 301 and 311-313 is approximately equalto the thickness of a conventional pre-metal dielectric structure.

Note that in an alternate embodiment, one or more additional dielectriclayers (such as silicon oxide) can be fabricated between first pre-metaldielectric layer 311 and amorphous silicon layer 312 to suppress theout-diffusion of impurities from the first pre-metal dielectric layer311 to amorphous silicon layer 312. Similarly, one or more additionaldielectric layers can be fabricated between amorphous silicon layer 312and second pre-metal dielectric layer 313 to suppress the out-diffusionof impurities from the second pre-metal dielectric layer 313 toamorphous silicon layer 312. Preventing the diffusion of impurities toamorphous silicon layer 312 advantageously minimizes the conductance ofthis layer 312.

As illustrated in FIG. 3C, a photoresist mask 320 having openings321-326 is formed over second pre-metal dielectric layer 313. Openings321-326 define the locations of contacts to be formed to underlyingcircuit elements. A series of etches is performed through openings321-326, thereby forming contact openings 331-336, as illustrated inFIG. 3D. Contact openings 331-336 extend through second pre-metaldielectric layer 313, amorphous silicon layer 312 and first pre-metaldielectric layer 311, and stop on silicon nitride layer 301.

In accordance with one embodiment, etches are performed to remove theexposed portions of silicon nitride layer 301 (and the associatedportions of the underlying gate dielectric layer 103) at the bottom ofcontact openings 331-336. As shown in FIG. 3E, photoresist mask 320 isstripped, and electrically conductive contacts C1-C6 are formed incontact openings 331-336 using conventional process steps. Thesecontacts C1-C6 provide electrical connections to the structures (e.g.,N-type regions 121-123, P-type regions 111-112 and control gate 140)exposed by contact openings 331-336. Contacts C1-C6 can be formed, forexample, by aluminum or tungsten. A thin barrier/adhesion layer (e.g.,Ti/TiN) (not shown) can be deposited in contact openings 331-336 beforecontacts C1-C6 are formed.

A first metal layer is then deposited over the resulting structure.Another photoresist mask (not shown), which defines the desired patternof the first metal layer, is formed over the first metal layer. An etchis performed through this photoresist mask, thereby patterning the firstmetal layer to create the metal traces M1-M6 illustrated in FIG. 3E.Note that metal traces M1 and M5 can be joined outside of the crosssection of FIG. 3E. The photoresist mask is then stripped, and the backend processing continues, with the alternating formation of dielectriclayers, vias and patterned metal layers.

Note that after amorphous silicon layer 312 is formed, the underlyingfloating gate 130 is protected from UV radiation present duringsubsequent processing steps and during normal operation of the resultingsingle-poly EEPROM cell 100. Consequently, UV radiation does not resultin a change in the charge stored by floating gate 130 (e.g., a transferof electronic charge between floating gate 130 and control gate 140, orbetween N and P wells 115 and 125). As a result, EEPROM cell 100 isresistant to tamper attacks that rely on UV irradiation.

It is also important to note that in the described embodiment, theresistance of amorphous silicon layer 312 is high enough to preventcontacts C1-C6 from being electrically shorted through the amorphoussilicon layer 312.

FIGS. 4A and 4B are cross-sectional views of EEPROM cell 100 inaccordance with one variation of the above-described embodiment. Inaccordance with this embodiment processing is performed as describedabove in connection with FIGS. 3A-3D (and photoresist mask 320 isstripped). An in-situ steam generation (ISSG) oxidation step is thenperformed, thereby forming silicon oxide regions 341-346 on the exposedsidewalls of amorphous silicon layer 312. The resulting structure isillustrated in FIG. 4A. In the ISSG process, the structure of FIG. 3D isplaced in a cold wall chamber with a mixture of hydrogen and oxygen.Wafer is heated by power radiation (RTP), thereby allowing the growth ofoxide at the exposed surfaces of the amorphous silicon layer 312 using avery low thermal budget. Note that standard thermal processes wouldlikely result in dopant diffusion and the sealing of contact openings331-336. After silicon oxide regions 341-346 are formed, processingcontinues as described above in connection with FIG. 3E, thereby formingcontacts C1-C6. Silicon oxide regions 341-346 help ensure that thesubsequently formed contacts C1-C6 are not shorted by amorphous siliconlayer 312. The resulting structure is shown in FIG. 4B.

FIGS. 5A, 5B and 5C are cross-sectional views of EEPROM cell 100 inaccordance with another variation of the above-described embodiment. Inaccordance with this variation, processing is performed as describedabove in connection with FIGS. 3A-3D (photoresist mask 320 is stripped).A chemical vapor deposition (CVD) step is performed, such that a CVDdielectric layer 501 is deposited over the resulting structure (and intocontact openings 331-336). In one embodiment, CVD dielectric layer 501is tetra-ethoxy-silane (TEOS) having a thickness of about 60 to 100Angstroms on the walls of contact openings 331-336. The resultingstructure is shown in FIG. 5A. When depositing the TEOS film 501, theactual thickness on the top of BPSG layer 313 is higher than on thewalls of the contact opening.

A directional (vertical) etch is then performed to remove the portionsof CVD dielectric layer 501 located on the horizontal surfaces of theresulting structure. The parameters for such a directional etch areknown to those of ordinary skill in the art. The resulting structureafter the directional etch is complete is shown in FIG. 5B. Processingcontinues as described above in connection with FIG. 3E, such thatcontacts C1-C6 are formed. The remaining (un-etched) portions of CVDdielectric layer 501 help ensure that the subsequently formed contactsC1-C6 are not shorted by amorphous silicon layer 312. The resultingstructure is shown in FIG. 5C.

FIG. 6 is a cross-sectional view of EEPROM cell 100 in accordance withyet another variation of the above-described embodiments. In thisvariation, both silicon oxide regions 341-346 and CVD dielectric layer501 are formed prior to forming contacts C1-C6. The presence of bothsilicon oxide regions 341-346 and CVD dielectric layer 501 furtherensure that contacts C1-C6 are not shorted by amorphous silicon layer312.

In accordance with a second embodiment of the present invention,amorphous silicon layer 312 is patterned before the second pre-metaldielectric layer 313 is formed. This embodiment undesirably requires anadditional masking step when compared with the above-describedembodiments and variations. In the second embodiment, which is describedin more detail below, first pre-metal dielectric layer 311 and amorphoussilicon layer 312 are formed as described above in connection with FIGS.3A and 3B.

FIGS. 7A, 7B, 7C and 7D are cross-sectional views of single-poly EEPROMcell 100 in accordance with the second embodiment. As illustrated inFIG. 7A, after first pre-metal dielectric layer 311 and amorphoussilicon layer 312 have been formed (and before the second pre-metaldielectric layer is formed) a photoresist mask 720 is formed overamorphous silicon layer 312. Photoresist mask 720 includes openings721-726, which generally define the locations of the contacts to beformed to underlying circuit elements. Openings 721-726 are larger thanthe openings which are subsequently formed for the contacts. Forexample, openings 721-726 may have a diameter of about 0.4 microns,while the openings subsequently used to form the contacts may have adiameter of about 0.22 microns. A series of etches is performed throughopenings 721-726, thereby forming dielectric openings 731-736, asillustrated in FIG. 7B. Dielectric openings 731-736 extend throughamorphous silicon layer 312 and stop on first pre-metal dielectric layer311. Dielectric openings 731-736 may extend into first pre-metaldielectric layer 311, without adverse effects.

Photoresist mask 720 is stripped, and a second pre-metal dielectriclayer 713 is formed over amorphous silicon layer 312, as illustrated inFIG. 7C. The second pre-metal dielectric layer 713 fills dielectricopenings 731-736. In the described embodiment, pre-metal dielectriclayer 713 can be BPSG deposited to a thickness in the range of 500 to8000 Angstroms (on the flat external surface). However, other dielectricmaterials and thicknesses can be used in other embodiments.

As illustrated in FIG. 7D, contacts C1-C6 are subsequently formed in themanner described above in connection with FIG. 3E. The contact openings331-336 are formed entirely within dielectric openings 731-736, suchthat portions of the second pre-metal dielectric layer 713 remain indielectric openings 731-736, laterally surrounding contacts C1-C6.Contacts C1-C6 therefore do not contact amorphous silicon layer 312.Rather, remaining portions of the second pre-metal dielectric layer 713in dielectric openings 731-736 serve to isolate contacts C1-C6 fromamorphous silicon layer 312.

In the above-described embodiments, amorphous silicon layer 312 has beenincorporated in the pre-metal dielectric layer. As a result, amorphoussilicon layer 312 is located relatively close to the underlyingsemiconductor structures. Advantageously, this provides improved UVblocking for the underlying semiconductor structures. In otherembodiments, the amorphous silicon layer can be formed in other back enddielectric layers (e.g., the first metal dielectric layer, the secondmetal dielectric layer, etc.). However, the higher the protectingamorphous silicon layer, the easier it is for a tamperer to remove thislayer and form electrical contacts to the chip.

Locating amorphous silicon layer 312 in the pre-dielectric layer ensuresthat attempts to de-process the resulting device by removing theamorphous silicon layer 312 will result in ruining the metal contactpads on top of the multi-layer interconnect structure. As a result,tamperers will be unable to switch the device electrically.

In addition, although the above described embodiments define contactplugs that are made at a different time than the first metal layer, itis understood that the contact plugs and first metal layer may befabricated at the same time, wherein a portion of the first metal layerfills the contact openings.

Advantageously, the present invention introduces minimal additionalprocess steps over a standard CMOS fabrication process. In addition, theamorphous silicon layer 301 does not add parasitic capacitance typicalfor conductive metal layer UV protection. Moreover, the amorphoussilicon layer 312 exhibits very good compatibility with advancedsub-micron CMOS fabrication processes.

Although the invention has been described in connection with severalembodiments, it is understood that this invention is not limited to theembodiments disclosed, but is capable of various modifications, whichwould be apparent to a person skilled in the art. For example, althoughthe present invention was described in terms of a single amorphoussilicon layer 312, it is understood that other numbers of amorphoussilicon layers can be used in other embodiments. In addition, thevarious described p-type regions can be interchanged with the describedn-type regions to provide similar results. Though the description wasbased on single-poly devices, a double-poly floating gate structure canbe protected in the same way. Moreover, other UV absorbing materials canbe used instead of amorphous silicon, including strongly siliconenriched oxides and nitrides or oxides and nitrides containing siliconclusters. Thus, the invention is limited only by the following claims.

1. A semiconductor device comprising: a semiconductor substrate; asingle patterned conductive gate layer that provides all gates of thesemiconductor device, including one or more floating gates located overthe semiconductor substrate; a first dielectric layer located over thepatterned conductive gate layer; an amorphous silicon layer located overthe first dielectric layer; and a second dielectric layer located overthe amorphous silicon layer.
 2. The semiconductor device of claim 1,wherein the patterned conductive gate layer further comprises one ormore control gates, each located adjacent to a corresponding one of thefloating gates.
 3. The semiconductor device of claim 2, wherein eachcontrol gate and the adjacent corresponding floating gate compriseinter-digitated regions.
 4. The semiconductor device of claim 2, whereineach control gate and the adjacent corresponding floating gate form aportion of an electrically erasable and programmable read only memory(EEPROM) cell.
 5. The semiconductor device of claim 1, wherein thepatterned conductive gate layer comprises polycrystalline silicon. 6.The semiconductor device of claim 1, further comprising one or moreelectrically conductive contacts that extend through the firstdielectric layer, the amorphous silicon layer and the second dielectriclayer, and contact the substrate.
 7. The semiconductor device of claim6, wherein the electrically conductive contacts are in contact with theamorphous silicon layer.
 8. The semiconductor device of claim 6, furthercomprising a first dielectric region located between each of theelectrically conductive contacts and the amorphous silicon layer.
 9. Thesemiconductor device of claim 8, further comprising a second dielectricregion located between each of the electrically conductive contacts andthe amorphous silicon layer, wherein the first and second dielectricregions have different compositions.
 10. The semiconductor device ofclaim 6, further comprising a patterned first metal layer located overthe second dielectric layer and in contact with the electricallyconductive contacts.
 11. The semiconductor device of claim 1, whereinthe amorphous silicon layer is in contact with the first and seconddielectric layers.
 12. The semiconductor device of claim 1, furthercomprising a first diffusion barrier layer located between the firstdielectric layer and the amorphous silicon layer layer.
 13. Thesemiconductor device of claim 12, further comprising a second diffusionbarrier layer located between the second dielectric layer and theamorphous silicon layer.
 14. The semiconductor device of claim 1,further comprising one or more electrically conductive vias that extendthrough the first dielectric layer, the amorphous silicon layer and thesecond dielectric layer, and contact a first metal layer located overthe substrate and a second metal layer located over the first metallayer.
 15. The semiconductor device of claim 14, wherein theelectrically conductive vias are in contact with the amorphous siliconlayer.
 16. The semiconductor device of claim 14, further comprising afirst dielectric region located between each of the electricallyconductive vias and the amorphous silicon layer.
 17. The semiconductordevice of claim 16, further comprising a second dielectric regionlocated between each of the electrically conductive vias and theamorphous silicon layer, wherein the first and second dielectric regionshave different compositions.
 18. The semiconductor device of claim 14,wherein the amorphous silicon layer is in contact with the first andsecond dielectric layers.
 19. The semiconductor device of claim 14,further comprising a first diffusion barrier layer located between thefirst dielectric layer and the amorphous silicon layer.
 20. Thesemiconductor device of claim 19, further comprising a second diffusionbarrier layer located between the second dielectric layer and theamorphous silicon layer.
 21. A method of fabricating a semiconductordevice, comprising: forming a single conductive gate layer over asurface of a semiconductor region; patterning the single conductive gatelayer to create a plurality of gate structures, including one or morefloating gates; forming a first dielectric layer over the gatestructures and the semiconductor region; forming an amorphous siliconlayer over the first dielectric layer; and forming a second dielectriclayer over the amorphous silicon layer.
 22. The method of claim 21,further comprising patterning the single conductive gate layer to createa control gate adjacent to each of the one or more floating gates. 23.The method of claim 21, wherein each control gate and adjacent floatinggate form a portion of an electrically erasable and programmable readonly memory (EEPROM) cell.
 24. The method of claim 21, wherein the stepof forming the single conductive gate layer comprises depositing a layerof polycrystalline silicon.
 25. The method of claim 21, furthercomprising: forming a plurality of contact openings through the firstdielectric layer, the amorphous silicon layer and the second dielectriclayer; and forming electrically conductive contacts in the contactopenings.
 26. The method of claim 25, wherein the step of forming theelectrically conductive contacts comprises forming the electricallyconductive contacts in contact with the amorphous silicon layer.
 27. Themethod of claim 25, further comprising forming a first dielectric regionat locations where the amorphous silicon layer is exposed by the contactopenings.
 28. The method of claim 27, further comprising forming thefirst dielectric region by in-situ steam generation (ISSG).
 29. Themethod of claim 27, further comprising forming the first dielectricregion by chemical vapor deposition (CVD).
 30. The method of claim 29,wherein the first dielectric region comprises tetra-ethoxy-silane(TEOS).
 31. The method of claim 27, further comprising forming a seconddielectric region over the first dielectric region, wherein the firstand second dielectric regions have different compositions.
 32. Themethod of claim 25, further comprising forming a patterned first metallayer over the second dielectric layer and in contact with theelectrically conductive contacts.
 33. The method of claim 32, whereinthe step of forming the electrically conductive contacts comprisescontacting the semiconductor region.
 34. The method of claim 32, furthercomprising forming a patterned second metal layer over the patternedfirst metal layer, wherein the electrically conductive contacts contactthe patterned first and second metal layers.
 35. The method of claim 21,further comprising forming the first dielectric layer, the amorphoussilicon layer and the second dielectric layer such that the amorphoussilicon layer is in contact with the first dielectric layer and thesecond dielectric layer.
 36. The method of claim 21, further comprisingforming a first diffusion barrier layer between the first dielectriclayer and the amorphous silicon layer.
 37. The method of claim 36,further comprising forming a second diffusion barrier layer between thesecond dielectric layer and the amorphous silicon layer.